1. Field of the Invention
This invention relates to oscillation state discrimination circuits that discriminate oscillation states of oscillation circuits such as crystal oscillators. In addition, this invention also relates to oscillation control circuits that control oscillation states and oscillation outputs of oscillation circuits, particularly in initial periods of oscillation.
2. Description of the Related Art
Conventionally, a variety of oscillation circuits using quartz oscillators (namely, crystal oscillators) have been widely used and installed in electronic devices, wherein quartz oscillators are reduced in sizes to match recent electronic devices, which tend to be compact and downsized to satisfy consumers' demands. Although quartz oscillators are reduced in sizes, they may be easily damaged due to excitation signals applied thereto. For this reason, so-called damping resistors are arranged for oscillation circuits to suppress levels of excitation signals exciting quartz oscillators so that oscillation states will be maintained in a stable manner.
Damping resistors operate to suppress excitations of quartz oscillators, wherein they have a drawback in that a relatively long time is required to stabilize oscillation states particularly in initial periods of oscillations just after applying electric power therefor. In order to solve the aforementioned drawback, a so-called damping resistance changeover method is adapted in such a way that damping resistors are controlled to be reduced in effective resistances in initial periods of oscillations; then, they are restored to original resistances thereof.
FIG. 13 shows an example of an oscillation circuit using a damping resistance changeover method that is conventionally known. Herein, a quartz oscillator XT defining an oscillation frequency is arranged between an input terminal and an output terminal of an inverter IA, which in turn functions as an inverting amplifier for exciting the quartz oscillator XT. A resistor Rf defining an operating point of the inverter IA is also arranged between the input terminal and output terminal of the inverter IA. To cause oscillation in the oscillation circuit of FIG. 13, a gain of the inverter IA in a small-amplitude mode should exceed a loss of the crystal oscillator XT. Therefore, the operating point of the inverter IA is set by adjusting the resistor Rf in order to produce a gain that may exceed the loss of the crystal oscillator XT.
A damping resistance Rd (i.e., a damping resistor having a resistance Rd that is controlled to be varied or switched over) is used to control a level of an excitation signal exciting the quartz oscillator XT, wherein a switch SW is used to change over the damping resistance Rd. Capacitors CA and CB are used to remove higher harmonics components from an oscillation waveform that is produced by exciting the quartz oscillator XT in the oscillation circuit. An oscillation signal appears on the output terminal of the inverter IA and is then subjected to waveform shaping in an inverter IV, which in turn produces a clock signal CKX. A timer circuit TM starts to measure a prescribed time period upon receipt of a trigger, i.e., a reset signal RST, wherein it outputs an window signal WIN having a high level during measurement. The aforementioned time period measured by the timer circuit TM may be sufficiently increased to include an unstable time period of oscillation (e.g., a transient time period of supply voltage).
The overall operation of the conventional oscillation circuit of FIG. 13 will be described below.
First, a description will be given with respect to a stable state of oscillation that is established upon elapse of a certain time after applying supply voltage. In this case, the timer circuit TM does not operate so that a contact of the switch SW is fixed to actualize a normal resistance for the damping resistor ‘Rd’, wherein the inverter IA and the quartz oscillator XT forms a negative feedback loop to cause oscillation, so that an oscillation signal appears on the output terminal of the inverter IA. When an oscillation frequency deviates from a characteristic frequency (or natural frequency) of the quartz oscillator XT, the quartz oscillator XT may indicate an inductive property or a capacitive property in response to a deviating direction of frequency. As a result, the oscillation frequency is stabilized in proximity to the characteristic frequency of the quartz oscillator XT, so that the inverter IB produces a clock signal CKX whose frequency may substantially match the characteristic frequency of the quartz oscillator XT. This clock signal CKX is supplied to circuitry (not shown) to operate.
Next, an unstable state of oscillation that occurs just after applying supply voltage will be described with reference to FIGS. 14A to 14C. At time t11, supply voltage VDD (see FIG. 14A) is applied to the oscillation circuit of FIG. 13, wherein it is gradually increased in level in response to a certain time constant. When the inverter IA starts amplification upon receipt of the supply voltage VDD, oscillation is started so that the inverter IB starts to produce a clock signal CKX (see FIG. 14B).
At time t11 when the supply voltage VDD is applied, the timer circuit TM may receive a reset signal RST from a system (not shown) that uses the oscillation circuit of FIG. 13, wherein the reset signal RST is produced by the system upon detection of applying the supply voltage VDD. Therefore, the timer circuit TM is reset by the reset signal RST and then starts counting a prescribed time period until time t12. During measurement, the timer circuit TM produces a window signal WIN (see FIG. 14C) having a high level, which may be sustained between time t11 and time t12. The window signal WIN is supplied to the switch SW, which is thus controlled in switching operation.
Specifically, the timer TM starts measuring time at time t11, so that the window signal WIN turns to a high level. In response to the window signal WIN, the switch SW is controlled to adequately switch over the contact thereof to reduce the damping resistance Rd. That is, suppression of an excitation level controlled by the damping resistance Rd is released so that oscillation is controlled to be rapidly stabilized. At time t12 when the timer circuit TM completes measuring a prescribed time period, the window signal WIN turns to a low level. At this time, the switch SW switches over the contact thereof so that the damping resistance Rd is restored to an original resistance thereof. Thus, it is possible to suppress an excitation level of the quartz oscillator XT to a certain level realizing oscillation to be maintained in a stable manner.
The prescribed time period measured by the timer circuit TM is set to include an unstable time period of oscillation (or a transient time period of supply voltage) as described above. That is, at time t12 when the switch SW is switched over, oscillation of the oscillation circuit has been already stabilized. Therefore, even when the damping resistance Rd is restored to an original resistance thereof, oscillation of the oscillation circuit would not become unstable so that oscillation is maintained in a stable manner.
In the conventional example of the oscillation circuit, the damping resistance Rd is reduced during a prescribed time period in an initial period of oscillation so that oscillation can be rapidly stabilized; then, after elapse of the prescribed time period, the damping resistance Rd is restored to an original resistance thereof so that oscillation will be maintained in a stable manner.
In the above, the time length of an unstable period of oscillation that emerges just after applying supply voltage to the oscillation circuit may highly depend upon uncertain elements such as time constants of a voltage supply (or a power supply). In order to securely restore the damping resistance Rd to an original resistance thereof after oscillation is certainly stabilized, it is necessary to increase the prescribed time period (i.e., a time measurement period of the timer circuit TM) to be sufficiently long. However, when the time measurement period of the timer circuit TM is set to be sufficiently long, the damping resistance Rd should be continuously reduced to a certain small resistance for a while even when oscillation is stabilized, which in turn increases an excitation level applied to the quartz oscillator XT. This causes a relatively intense stress on the quartz oscillator XT, which may be easily damaged. In addition, when an external device inputs an oscillation signal that is produced by the oscillation circuit whose oscillation is unstable, there is a possibility that the external device may operate abnormally.